Electrical power for an integrated circuit (IC) is typically supplied by one or more direct current (battery) power sources, such as a pulse width modulation (PWM)-based, DC-DC converter. As diagrammatically illustrated in FIG. 1, this type of converter contains a PWM signal generator 1 that supplies a synchronous PWM signal to a switching circuit driver 2. Such a PWM-based converter architecture is ideally intended to deliver constant energy to an output node regardless of the input voltage. To this end, the switching circuit driver 2 controls the on-time and off-time of a pair of electronic power switching devices 3 and 4 (typically external NFETs) connected between power supply rails Vin and ground (GND). A common or PHASE node 5 between the two FETs is coupled through an inductor 6 to a load reservoir capacitor 7, with the connection 8 between inductor 6 and capacitor 7 serving as an output node from which a desired (regulated) DC output voltage is applied to load 9.
The circuit of FIG. 1 typically operates in the manner shown in the set of timing diagrams of FIG. 2. In particular, in response to a positive-going transition 201 in a PWM waveform 200, the FET driver 2 turns off the LGATE drive to the lower FET 4. In response to the LGATE voltage 210 dropping to a prescribed threshold detection value 211 (e.g., 1.5 V), the driver control circuitry 2 applies a UGATE turn on voltage 220 which exhibits a positive excursion 221 to the gate drive input of the upper FET 3. The voltage at the PHASE node represented by signal trace 230 substantially follows the upper gate voltage signal and is monitored to control the turn-on of the LFET 4.
In particular, in response to a negative-going transition 202 in the PWM signal 200, the UGATE signal undergoes a high to low transition 222, turning off the UFET 3. Then, in response to the associated excursion 232 in the PHASE node voltage 230 dropping to a predetermined threshold detection value 233, the LGATE voltage is transitioned high, as shown by the positive-going excursion 212 of the LGATE signal 210, turning on the LFET 4. FIG. 2 also shows the application of a tristate or power-on reset signal 240 having rising edge 241 to turn off the lower gate drive signal at 213 and falling edge 242 to turn on the lower gate signal at 214.
In the course of terminating the on-time of each FET switch, it is desirable to provide a time interval during which both controlled switches (UFET 3 and LFET 4) are guaranteed to be off. This time interval, known as ‘dead time’, allows for the resetting of magnetic circuit components within the power supply. Namely, modulation of the PWM generator's duty cycle is limited, in order to insure that there always exists a dead time period. This also serves to prevent efficiency degradation, which occurs when both the upper and lower FETs intermittently conduct during a common time interval. This unwanted intermittent conduction problem results from insufficient dead time before the other FET begins conduction. Among factors that contribute to this phenomenon are the type of FET being used and board parasitic layout.